The present invention relates generally to very large scale integrated circuit devices, and more particularly to a VLSI design for significantly reducing the number of engineering change (EC) pads utilized in such devices.
The trend in very large scale integration devices is to increase the number of circuits per semiconductor chip. This increased number of crrcuits requires an increasing number of input and output terminals (I/O's) per chip in order to permit maximum utilization of these circuits in accordance with Rent's rule.
The electronics industry currently utilizes multilayered circuit packaging modules (typically ceramic) for carrying these large scale integrated circuit chips. These VLSI chips are mounted on the top surface of the module at selected chip sites. Each chip site is composed of a central array of chip connection vias (lead/tin solder balls or microsockets). These chip connection vias at the chip site are routed down through the various layers of the ceramic module and then are routed to various other chips on the module surface in order to communicate therewith. The signal redistribution lines between chip vias are generally formed by first punching holes in individual, flexible, unfired green sheets of soft ceramic layers and then printing or screening a patterning paste through a metal mask to form predetermined wiring patterns on the green sheet and to fill the various holes punched therein. The completed module is fabricated by stacking multiple green sheet layers together to form a semi-hard stack or laminate, which is then fired. The resulting structure is a high performance module for VLSI chips typically containing 60-70 wiring layers. However, defects such as opens in the via connections between green sheet layers, opens in the horizontal lines screened in the green sheets, and shorts between lines can occur during the green sheet stacking process used in forming the module. Accordingly, it is highly desirable to be able to correct such manufacturing defects in the module. Likewise, it is highly desirable to be able to make engineering changes to correct for design errors in the interconnections between the I/O's of various chips on the module.
In order to facilitate such defect corrections and engineering changes, engineering change (EC) pads are provided for each signal I/O terminal of the chip. The purpose of these EC pads is to allow the correction of these wiring defects by the deletion of the internal wiring and its replacement with discrete surface wires. A standard design for such EC pads is a deposit of metal in the shape of a dumbbell. The EC pad is located between the I/O terminal of the chip and a via which connects to internal wiring in the ceramic module. When it is desired to break the connection between this particular I/O terminal of the chip and the via connected to the internal wiring of the module, then the narrow portion between the dumbbells may be broken by means such as laser evaporation. This I/O terminal may then be connected to the I/O terminal of another chip by means of, for example, the ultrasonic bonding of a surface wire therebetween.
Currently, state-of-the-art multi-layer chip carrying modules utilize a separate EC pad for each chip I/O pad. These EC pads are generally disposed in concentric rings around the perimeter of each chip. Accordingly, as the number of circuits and their attendant I/O pads increase, the number of EC pads required around the perimeter of the chip increases correspondingly. The net result is that approximately half of the mounting surface on the module is allocated to EC pads and related spacings.
Attempts have been made to reduce the size of a typical 100 micron x 100 micron EC pad. However, the EC pad size is constrained by certain minimum area requirements imposed by the need to physically perform weld and delete operations at the pad.
The above-described EC requirements result in a significant loss of chip packing density. This loss in chip packing density causes a loss of module circuit capacity and thus higher circuit packaging costs, as well as delay.
The invention as claimed is intended to remedy the above-described drawbacks. It solves the problem of the increasing space required on the multilayer module for engineering change operations while at the same time, increasing the communication speed between chips.